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D-Phy Architecture:

D-Phy Architecture


Mixel’s D-PHY

Mixel’s D-PHY is a complete 1Gbps silicon-proven PHY  
Mixel’s D-PHY

Mixel's D-PHY is a complete PHY, silicon-proven at multiple foundries. The D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to interface with the Camera, Display and UniPro™ protocols (all MIPI standards) using the PHY Protocol Interface (PPI).

The Mixel D-PHY features:

  • The D-PHY uses point-to-point differential interface and has modular architecture supporting multiple data lanes and a clock lane allowing all possible configurations
  • Mixel’s D-PHY data lanes support both bidirectional and unidirectional modes, Clock lane supports unidirectional communication
  • The D-PHY supports 80Mbps to 1Gbps data rate in high speed mode, 10Mbps data rate in low-power mode

Mixel’s D-PHY is architected to mate perfectly with our high performance PLLs specifically designed to address MIPI applications up to 1Gbps.